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IPM6210A
TM
Data Sheet
August 2001
File Number
9033.1
Precision Dual PWM Controller And Linear Regulator for Notebook CPUs
The IPM6210A is a highly integrated power controller which provides a complete power management solution for mobile CPUs. The IC integrates two PWM controllers and a linear regulator as well as monitoring and protection circuitry into a single 28-lead plastic SSOP package. The two PWM controllers regulate the microprocessor core and I/O voltages with synchronous-rectified buck converters, while the linear regulator powers the CPU clock. The IPM6210A includes 5-bit digital-to-analog converter (DAC) that adjusts the core PWM output voltage from 0.925V DC to 2.0VDC and conforms to the Intel Mobile VID specification. The DAC setting may be changed during operation to accommodate Dual-Mode processors. Special measures are taken to provide such a transition with controlled rate in a specified 100s. A precision reference, remote sensing, and a proprietary architecture with integrated processor mode-compensated "droop" provide excellent static and dynamic core voltage regulation. The second PWM controller has a fixed 1.5V output voltage and powers the I/O circuitry. Both PWM controllers have integrated feedback loop compensation that dramatically reduces number of the external components. At nominal loads PWM controllers operate at a fixed frequency of 300kHz. At light loads when the filter inductor current becomes discontinuous, controllers operate in a hysteretic mode. Out-of-phase operation of two PWM controllers to reduce input current ripple is provide in both modes of operation. The linear regulator uses an internal pass device to provide 2.5V for the CPU clock generator. The IPM6210A monitors all the output voltages. A single Power-Good signal is issued when soft start is completed and all outputs are within 10% of their respective set points. A built-in overvoltage protection for the core and I/O outputs forces the lower MOSFETs on to prevent output voltages from going above 115% of their settings. Undervoltage protection latches the chip off when any of three outputs drops below 75% of the set value. The PWM controller's overcurrent circuitry monitors the output current by sensing the voltage drop across the lower MOSFETs. If precision overcurrent protection is required, an external current-sense resistor may optionally be used.
Features
* Provides 3 Regulated Voltages - 0.9V to 2.0V Microprocessor Core (SpeedStepTM Enabled) - 1.5V Microprocessor I/O - 2.5V Microprocessor Clock Generator * High Efficiency Over Wide Load Range * Not Dissipative Current-Sense Scheme - Uses MOSFET's rDS(ON) - Optional Current-Sense Resistor for Precision Overcurrent * Adaptive Dead-Time Drivers for N-Channel MOSFETs * Operates from +5V, +3.3V and Battery (5.6-24V) Inputs * Precision Core Voltage Control: - Remote "Kelvin" Sensing - Summing Current-Mode Control - On-Chip Mode-Compensated "Droop" for Optimum Transient Response and Lower Processor Power Dissipation * TTL-Compatible 5-Bit Digital Output Voltage Selection - Wide Range - 0.925V DC to 1.3VDC in 25mV Steps, and from 1.3VDC to 2.0VDC in 50mV Steps - Programmable "On-the-Fly" VID Code Change with Customer Programmable Slew Rate and 100s Settling Time * Power-Good Output Voltage Monitor * No Negative Voltage on Outputs at Turn-Off * Overvoltage, Undervoltage and Overcurrent Fault Monitors * 300kHz Fixed Switching Frequency * Thermal Shutdown
Applications
* Mobile PCs * Web Tablets * Internet Appliances
Ordering Information
PART NUMBER IPM6210ACA IPM6210ACA-T TEMP. (oC) -10 to 85 -10 to 85 PACKAGE 28 Ld SSOP 28 Ld SSOP, Tape and Reel PKG. NO. M28.15 M28.15
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. SpeedStepTM is a trademark of Intel Corporation. | Copyright (c) Intersil Americas Inc. 2001, All Rights Reserved
IPM6210A Pinout
IPM6210A (SSOP) TOP VIEW
LGATE2 1 PGND2 2 BOOT2 3 UGATE2 4 PHASE2 5 ISEN2 6 VID4 7 VID3 8 VID2 9 VID1 10 VID0 11 VSEN2 12 V3IN 13 VOUT3 14 28 VCC 27 LGATE1 26 PGND1 25 BOOT1 24 UGATE1 23 PHASE1 22 ISEN1 21 PGOOD 20 EN 19 VIN 18 SOFT 17 VSEN1 16 VRET1 15 GND
Simplified Power System Diagram
+VIN
PWM2 VOUT2 I/O CONTROLLER
PWM1 CONTROLLER VOUT1 CORE
+VIN 3.3V VOUT3 CPU CLK
LINEAR REGULATOR
VID CODE
IPM6210A
2
IPM6210A
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.5V Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +27.0V V3in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.5V PHASE1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +33.0V BOOT1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +33.0V BOOT1,2 with respect to PHASE1,2 . . . . . . . . . . . . . . . . . . . . . +6.5V PGOOD, RT/FAULT, and GATE Voltage . . . .GND - 0.3V to VCC +0.3V Core Output or I/O Voltage . . . . . . . . . . . . . . . GND - 0.3V to +6.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Information
Thermal Resistance (Typical, Note 1)
JA (oC/W)
SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SSOP - Lead Tips Only)
Recommended Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.0V 5% Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.5V to 24.0V V3in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.3V 10% Ambient Temperature Range . . . . . . . . . . . . . . . . . . . -10oC to 85oC Junction Temperature Range. . . . . . . . . . . . . . . . . . -10oC to 125oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER VCC SUPPLY Nominal Supply Current Shutdown Supply Current Battery Pin Supply Current
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3 SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
ICC ICCS IVIN IVINSD
GATE1, GATE2 Open
30 -
2 30 -
2.5 200 1
mA A A A
Battery Pin Leakage Current at Shutdown POWER-ON RESET Rising VCC Threshold Falling VCC Threshold OSCILLATOR Free Running Frequency Ramp Amplitude, peak-to-peak Ramp Offset REFERENCE, DAC AND SOFT START VID0-VID4 Input Low Voltage VID0-VID4 Input High Voltage VID0-VID4 Pull-up Current to VCC DAC Voltage Accuracy Soft-Start Current During Start-Up Soft-Start Current During Mode Change ENABLE Enable Voltage Low Enable Voltage High
4.3 3.9
4.5 4.1
4.6 4.3
V V
255 VBAT = 16V -
300 2 0.5
345 -
kHz V V
1.8 -1.0 ISS ISSM VENLOW VENHIGH VSS = 0V...0.9V VSS = 0.925V...2.0V IC Inhibited IC Enabled Input has Internal Pull-up Current Source 2A (Typ) 18 350
1 25 500
1.2 +1.0 32 650
V V A % A A
2.0
-
1.2 -
V V
PWM 1 CONVERTER Output Voltage Static Load Regulation VOUT1 Defined by the current VID code (Table 1) 100mA < IVOUT1 < 15.0A 0.925 -2.0 2.0 +2.0 V %
3
IPM6210A
Electrical Specifications
PARAMETER Undervoltage Shutdown Level Undervoltage Shutdown Delay Overvoltage Overvoltage Shutdown Delay Overcurrent Comparator Threshold PWM 2 CONVERTER Output Voltage Load Regulation Undervoltage Shutdown Level Undervoltage Shutdown Delay Overvoltage Shutdown Overvoltage Shutdown Delay Overcurrent Comparator Threshold LINEAR REGULATOR Output Voltage Load Regulation Undervoltage Shutdown Level Current Limit PWM CONTROLLER ERROR AMPLIFIERS DC Gain Gain-Bandwidth Product Slew Rate PWM 1 CONTROLLER GATE DRIVERS Upper Drive Pull-Up Resistance Upper Drive Pull-Down Resistance Lower Drive Pull-Up Resistance Lower Drive Pull-Down Resistance PWM 2 CONTROLLER GATE DRIVERS Upper Drive Pull-Up Resistance Upper Drive Pull-Down Resistance Lower Drive Pull-Up Resistance Lower Drive Pull-Down Resistance POWER GOOD V OUT1 Upper Threshold VOUT1 Lower Threshold, Falling Edge VOUT1 Lower Threshold, Rising Edge VOUT2 Upper Threshold V OUT2 Lower Threshold V OUT3 Upper Threshold VOUT3 Lower Threshold PGOOD Voltage Low PGOOD Leakage Current VPGOOD IPGlLKG IPGOOD = -4mA VPULLUP = 5.0V Percent of the voltage defined by the VID code Percent of the voltage defined by the VID code Percent of the voltage defined by the VID code 108 85 87 1.63 1.32 2.7 2.18 114 92 94 1.7 1.38 2.9 2.32 0.5 1.0 % % % V V V V V A R2UGPUP R2UGPDN R2LGPUP R2LGPDN 12 6 10 3 20 10 20 5 R1UGPUP R1UGPDN R1LGPUP R1LGPDN 6 3 6 0.8 8 5 8 1.5 GBWP SR By Design By Design By Design 86 2.7 1 dB MHz V/s VUV3 Ioc3 VOUT3 1mA < IVOUT3 < 100mA -2.0 1.8 260 2.5 320 2.0 2.0 400 V % V mA VUV2 TDOC2 VOVP2 TDOV2 IOC2 VOUT2 100mA < IVOUT3 < 2.1A -2.0 1.09 1.2 1.70 1.6 100 1.5 140 +2.0 1.13 1.6 1.78 3.2 170 V % V s V s A Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3 (Continued) SYMBOL VUV1 TDOC1 VOVP1 TDOV1 IOC1 Percent of the voltage set by VID code. TEST CONDITIONS Percent of the voltage set by VID code. Disabled during dynamic VID code change. MIN 72 1.2 112 1.6 100 TYP 75 115 135 MAX 78 1.6 120 3.2 170 UNITS % s % s A
4
Block Diagram
VBAT EN BOOT1 HGDR1 HI FFBK1 RAMP 2 CLK RAMP 1 RESET (POR) GATE LOGIC 1 CLK2 CLK1 FCCM DEADT PWM/HYST LGDR1 LO OVP1 HYST COMP1 LGATE1 PGND1 PWM ON HYST ON HI OC COMP1 SHUTOFF GATE CONTROL VCC POWER-ON SHUTOFF UGATE1 PHASE1 VCC GND
LINEAR REGULATOR
V3IN
-
VOUT3
0.9V
BOOT2
HGDR2
UGATE2
-
+
+
+
+
EA2
VSEN2
-
0.9V DYNAMIC DUTY CYCLE CLAMP
+
-
+
+
MODE CONTROL COMP 2
+ -
DACOUT
+
5 + + VCC PWM LATCH 1 OC LOGIC1
+
PHASE2 GATE LOGIC 2 QD R Q<
CLK1 DAC OUT
-
GATE CONTROL DEADT PWM/HYST LO + HYST ON PWM ON
PRE AMP EA1
VCC
+
LGDR2
-
LGATE2
DYNAMIC DUTY CYCLE CLAMP
+
VSEN1
VRET1
OVP2
IPM6210A
PGND2
HYST COMP2 FFBK1 LGATE1 OC COMP2 2.8V
+ FAST FEEDBACK COMP1
-
CLK2
-
R1 = 20K MODE CONTROL PHASE1 LOGIC 1
LGATE1
OC LOGIC2 VCC PWM LATCH 2
+
ISEN1
+-
DQ R OUTPUT VOLTAGE MONITOR
OVP1
LGATE2 MODE PHASE1 CONTROL LOGIC 1
R1 = 20K LGATE2
OVP2
FCCM
TTL DAC REFERENCE SOFT START
ISEN2
-
PGOOD
VID0 VID1 VID2
VID3 VID4 SOFT
IPM6210A Functional Pin Descriptions
VID0, VID1, VID2, VID3, VID4 (Pins 11, 10, 9, 8 and 7 Respectively)
VID0-VID4 are the input pins to the 5-bit DAC. The states of these five pins program the internal voltage reference (DACOUT). The level of DACOUT sets the core converter output voltage (V OUT1). It also sets the core PGOOD, UVP and OVP thresholds.
VSEN1, VRTN1 (Pins 17 and 16)
These pins are connected to the core converter's output voltage to provide remote sensing. The PGOOD, UVP and OVP comparators use these pins for protection.
SOFT (Pin 18)
Connect a capacitor from this pin to the ground. This capacitor (typically 0.1mF), along with an internal 25mA current source, sets the soft-start interval of the converter. When voltage on this pin exceeds 0.9V, the soft start is completed. After the soft-start is completed, the pin function is changed. The internal circuit regulates voltage on this pin to the value commanded by VID code. The pin now has 500mA source/sink capability that allows to set desired slew rate for upward and downward VID code changes.
BOOT1, BOOT2 (Pins 25 and 3)
These pins provide power to the upper MOSFET drivers of the core and I/O converters. Connect these pins to their respective junctions of the bootstrap capacitors and the cathodes of the bootstrap diodes. The anodes of the bootstrap diodes are connected to pin 28, VCC.
PHASE1, PHASE2 (Pins 23 and 5)
The PHASE nodes are the junction points of the upper MOSFET sources, output filter inductors, and lower MOSFET drains. Connect the PHASE pins to the respective PWM converter's upper MOSFET source.
VIN (Pin 19)
VIN provides battery voltage to the oscillator for feed-forward rejection of input voltage variations.
EN (Pin 20)
This pin enables IC operation when left open or pulled-up to VCC. Also, it unlatches the chip after fault when being cycled.
ISEN1, ISEN2 (Pins 22 and 6)
These pins are used to monitor the voltage drop across the lower MOSFETs for current feedback, output voltage droop and overcurrent protection. For precise current detection these inputs could be connected to optional current sense resistors placed in series with sources of the lower MOSFETs. To set the gain of the current sense amplifier, a resistor should be placed in series with each of these inputs.
PGOOD (Pin 21)
PGOOD is an open drain output used to indicate the status of the PWM converters' output voltages. This pin is pulled low when the core output is not within 10% of the DACOUT reference voltage, or when any of the other outputs are not within their respective undervoltage and overvoltage thresholds. The PGOOD output is pulled low for "01111" and `11111' VID code. See Table 1.
UGATE1, UGATE2 (Pins 24 and 4)
These pins provide the gate drive for the upper MOSFETs.
LGATE1, LGATE 2 (Pin 27 and 1)
These pins provide the gate drive for the lower MOSFETs.
GND (Pin 15)
Signal ground for the IC. All voltage levels are measured with respect to this pin.
PGND1, PGND2 (Pin 26 and 2)
These are the power ground connection for the core and I/O converters, respectively. Tie each lower MOSFET source to the corresponding pin.
VCC (Pin 28)
Supplies all the power necessary to operate the chip. The IC starts to operate when the voltage on this pin exceeds 4.5V and shuts down when the voltage on this pin drops below 4.0V.
VSEN2 (Pin 12)
This pin is connected to the I/O output and provides voltage feedback to the I/O error amplifier. The PGOOD, UVP and OVP comparators use this signal.
Description
Operation Overview
The IPM6210A three-in-one power management integrated circuit provides complete power solution for modern processors for notebook and sub-notebook PCs. The IC controls operation of two synchronous buck converters and one linear regulator. The output voltage of the core converter can be adjusted in the range from 0.925V to 2.0 by changing the DAC code settings (see Table 1). The output voltage of the I/O converter is fixed to 1.5V. The internal linear regulator provides fixed 2.5V for the CPU clock generator from the system +3.3V bus. The output voltage of the core converter
V3IN (Pin 13)
This pin provides input power for the 2.5V linear regulator. The typical input voltage for that pin is 3.3V. Alternatively, 5.0V system rail can be used while efficiency will be proportionally lower.
VOUT3 (Pin 14)
Output of the 2.5V linear regulator. Supplies current up to 150mA. The output current on this pin is internally limited to 250mA.
6
IPM6210A
can be changed on-the-fly with programmable slew rate, which makes it especially suitable for the processors that feature modern power savings techniques as SpeedStepTM or PowerNow!TM . Both, core and I/O converters can operate in two modes: fixed frequency PWM and variable frequency hysteretic depending on the load level. At loads lower than the critical where filter inductor current becomes discontinuous, hysteretic mode of operation is activated. Switchover from PWM to hysteretic operation at light loads improves the converters' efficiency and prolongs battery run time. In hysteretic mode, comparators are synchronized to the main clock that allows seamless transition between the operational modes and reduced channel-to-channel interaction. As the filter inductor resumes continuous current, the PWM mode of operation is restored. The core converter incorporates Intersil's proprietary output voltage droop for optimum handling of fast load transients found in modern processors. The droop is compensated for the processor mode changes, which allows for relatively equal droop in any operation mode and to specify the droop as a fraction of the VID set voltage.
1
2 3 4
Ch1 VCPU 500mV Ch2 VIO 500mV Ch4 V EN 5.0V Ch3 VCLK 1.0V
M1.00ms VIN = 20V
FIGURE 1. INITIAL STARTUP
The value of the soft-start capacitor can be estimated by the following equation:
Issm Css = ------------------ t Vdac
For the typical conditions when DVdac = 0.25V, Dt = 100s:
500mA Cs s = -------------------100s = 0.2F 0.25V
Initialization
The IPM6210A initializes upon receipt of input power assuming EN is high or not connected. The Power-On Reset (POR) function continually monitors the input supply voltage on the VCC pin and initiates soft-start operation after input supply voltage exceeds 4.5V. Should this voltage drop lower than 4.0V, POR disables the chip.
With this value of the soft-start capacitor, soft start time will be equal to:
0.2Fx0.9V Tss = -------------------------------- = 7.2ms 25A
OUT1 Voltage Program
This output of PWM1 converter is designated to supply the microprocessor core voltage. The OUT1 voltage is programmed to discrete levels between 0.925VDC and 2.0VDC as specified in Table 1. The voltage identification (VID) pins program an internal voltage reference (DAC) through a TTL-compatible 5-bit digital-to-analog converter. The level of the DAC voltage also sets the PGOOD, UVP and OVP thresholds. The VID pins can be left open for a logic 1 input due to internal 1A pull-up to VCC . The `11111' and `0111` VID codes, as shown in Table 1, shut the IC down and set PGOOD low.
Soft-Start
When soft start is initiated, the voltage on the SOFT pin starts to ramp gradually due to the 25A current sourced into the external capacitor. When SOFT-pin voltage reaches 0.9V, the value of the sourcing current rapidly changes to 500A charging the softstart capacitor to the level determined by the DAC. This completes the soft start sequence, Figure 1. As long as the SOFT voltage is above 0.9V, the maximum value of the internal soft-start current is set to 500A allowing fast rate-ofchange in the core output voltage due to a VID code change. In this mode SOFT has both sourcing and sinking capabilities to maintain voltage across the soft-start capacitor conforming to the VID code. This dual slope approach helps to provide safe rise of voltages and currents in the converters during initial start-up and at the same time sets a controlled speed of the core voltage change when the processor commands to do so. Soft-start circuits for the I/O converter is slaved to the core output soft-start circuit and they complete their ramp-up when voltage on the SOFT pin reaches 0.9V.
Core Converter PWM Operation
At the nominal current core converter operates in a fixed frequency PWM mode. The output voltage is compared with a reference voltage set by the DAC. The derived error signal is amplified by an internally compensated error amplifier and applied to the inverting input of the PWM comparator. To provide output voltage droop for enhanced dynamic load regulation, a signal proportional to the output current is added to the voltage feedback signal. This feedback scheme in conjunction with a PWM ramp proportional to the input voltage allows for fast and stable loop response over a wide range of input voltage and output current variations. For the sake of efficiency and maximum simplicity, the current sense signal is derived from the voltage drop across the lower MOSFET during its conduction time.
SpeedStepTM is a trademark of Intel Corporation. PowerNow!TM is a trademark of Advanced Micro Devices, Inc.
7
IPM6210A
TABLE 1. PIN NAME VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 NOTE: 2. 0 = Connected to GND or VSS, 1 = open or connected to 3.3V through pull-up resistors. VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 NOMINAL OUT1 VOLTAGE 2.00 1.95 1.90 1.85 1.80 1.75 1.70 1.65 1.60 1.55 1.50 1.45 1.40
1.6 VCPU PERFORMANCE MODE
Mode-Compensated Droop
An output voltage `droop' or an active voltage positioning is now widely used in the computer power applications. The technique is based on raising the converter voltage at light load in anticipation of the possible load current step. Inversely, the output voltage is lowered at high load in anticipation of possible load drop. The output voltage varies with the load like it is a resistor connected in series with the converter's output. When done as a part of the feedback in a closed loop, the `droop' is not associated with substantial power losses, though. There is no such a resistor in a real circuit, but the feature is rather emulated by the feedback. The `droop' allows a reduction in size and cost of the output capacitors required to handle the transient. Additionally, the CPU power dissipation is also slightly reduced as it is proportional to the applied voltage squared and even a slight voltage decrease translates to a measurable reduction in power dissipated.
1.35 1.30 No CPU 1.275
1.35 BATTERY-OPTIMIZED MODE TRADITIONAL DROOP
1.250 1.225
MODE-COMPENSATED DROOP
1.200 1.175 1.150 1.125 1.100 1.075 1.050 1.025 1.000 0.975 0.950 0.925 No CPU
0 5 10 ICPU
FIGURE 2. MODE-COMPENSATED DROOP
When powering the dual mode processor, it is desired to have an adequate "droop" (equal fractions of the programmed output voltage) in both performance and battery-optimized modes of operation. The traditional "droop" is normally tuned to the worse case load, which is associated with the performance mode. In the battery optimized mode, the CPU operating voltage and the clock frequency are both scaled down. Due to the constant gain in the current loop, the traditional `droop' compensates only for the operating voltage change. The degree of the droop achieved in this case is not the same because the CPU current is significantly lower as it is illustrated by the following equation.
I C PU = KCPU x VCPUi xFCPUi x KF ;
Where, KCPU is a processor constant; VCPUi is processor operating voltage; FCPUi is processor clock frequency; KF is a coefficient that varies from 0 to 1 and indicates how heavily the processor is engaged by the software; i is a denominator associated with the processor mode of operation (performance or battery optimized).
8
IPM6210A
This resistor sets the gain in the current feedback loop. The droop is scaled to 5.5% of the VID code when current into ISEN1 pin equals 75A. The output voltage waveforms with droop subjected to load step are shown on Figures 3 through 5.
1
VCPU = 1.6V
1
VCPU = 1.00V
I CPU = 0.3A>>18A 2
Ch1 50mV
Ch2 5.0A
M50s
FIGURE 3.
This leads to deterioration of the droop benefits in the battery-optimized mode where they are mostly appreciable, Figure 2.
ICPU = 0.3A>>12.0A 2
Ch1 50mV 1 VCPU = 1.35V
Ch2 5.0A
M50ms
FIGURE 5.
Feedback Loop Compensation
Due to implemented average current mode control, the modulator has a single pole response with -1 slope at frequency determined by load:
1 FPO = ------------------------------- , 2xR O xC O
ICPU = 0.3A>>13.5A 2
Ch1 50mV
Ch2 5.0A
M50ms
FIGURE 4.
where RO is load resistance; CO is load capacitance. For this type of modulator Type 2 compensation circuit is usually sufficient. To reduce number of external components and remove the burden at determining compensation components from a system designer, both PWM controllers have internally compensated error amplifiers. Figure 6 shows Type 2 amplifier and its response along with responses of current mode modulator and the converter. The Type 2 amplifier, in addition to the pole at origin, has a zero-pole pair that causes a flat gain region at frequencies in between the zero and the pole.
1 F Z = ----------------------------- = 6kHz ; 2xR 2 xC 1 1 F P = ----------------------------- = 600k Hz ; 2xR 1 xC 2
The IPM6210A incorporates a new proprietary droop technique specially designed for the SpeedStepTM - enabled converters and provides mode-compensated, relatively equal droop in both, the performance and the batteryoptimized modes. The droop is set as a fraction of the VID programmed voltage and the gain in the current loop is different for each VID combination. That makes the droop compensated for the voltage and the frequency changes associated with the different CPU modes of operation. To accommodate the droop the output voltage of core converter is raised 2% at no load conditions. The resistor connected to ISEN1 pin programs the amount of droop.
I MAX xr DS ( ON ) R C S = --------------------------------------- - 100 75A
This region is also associated with phase `bump' or reduced phase shift. The amount of phase shift reduction depends on how wide the region of flat gain is and has a maximum value of 90 degrees. To further simplify the converter compensation, the modulator gain is kept independent of the input voltage variation by providing feed-forward of VIN to the oscillator ramp.
9
IPM6210A
C2 R2 C1
CONVERTER
R1
hysteretic mode. If during this pulse counting process the comparator's output happens to be high, the counter of the delay circuit will be reset and circuit will continue to monitor for eight low-level pulses in a row, as shown in Figure 7.
EA
TYPE 2 EA GEA = 18DB
MODULATOR
VOUT
t
GEA = 14dB FZ FP FC IIND t
FPO
PHASE COMP 12345 678 MODE OF OPERATION PWM HYSTERETIC t t
FIGURE 6.
The zero frequency, the amplifier high-frequency gain and the modulator gain are chosen to satisfy most of typical applications. The crossover frequency will appear at the point where the modulator attenuation equals the amplifier high frequency gain. The only task that the system designer has to complete is to specify the output filter capacitors to position the load main pole somewhere within one decade lower than the amplifier zero frequency. With this type of compensation plenty of phase margin is easily achieved due to zero-pole pair phase `boost'. Conditional stability may occur only when the main load pole is positioned too much to the left side on the frequency axis due to excessive output filter capacitance. In this case, the ESR zero placed within 10kHz...50kHz range gives some additional phase `boost'. Fortunately, there is an opposite trend in mobile applications to keep the output capacitor as small as possible.
FIGURE 7. PWM TO HYSTERETIC TRANSITION
VOUT
t
IIND 1 PHASE COMP 2 345 678
t
t HYSTERETIC PWM t
MODE OF OPERATION
FIGURE 8. HYSTERETIC TO PWM TRANSITION
Automatic Operation Mode Control
The mode control circuit changes the converter's mode of operation depending on the level of the load current. At nominal current the converter operates in a fixed frequency PWM mode. When the load current drops lower than the critical value, inductor current becomes discontinuous and the operation mode is changed to hysteretic. The mode control circuit consists of a flip-flop which provides HYST and NORMAL signals. These signals inhibit normal PWM operation and activate hysteretic comparator and diode emulation mode of the synchronous MOSFET. The inputs of the flip-flop are controlled by the outputs of two delay circuits that constantly monitor output of the phase node comparator. High level on the comparator output during PWM cycle is associated with continuous mode of operation. The low level -- corresponds to the discontinuous mode of operation. When the low level on the comparator output is detected eight times in a row, the mode control flipflop is set and converter is commanded to operate in the
The circuit which restores normal PWM operation mode works in the same way and is looking for eight in a row high-level pulses on the comparator's output. If during this counting process the comparator's output happens to be low, the counter will be reset and the mode control flip-flop will not change the state. The operation mode will only be changed when eight pulses in a row fill the counter, see Figure 8. This technique prevents jitter and chatter of the operation mode control logic at the load levels close to the critical.
Hysteretic Operation
When discontinuous inductor current is detected, the mode control logic changes the way the signals in the chip are processed by entering hysteretic mode. The comparator and the error amplifier that provided control in the PWM mode are inhibited, and the hysteretic comparator is now activated. Changes are also made to the gate logic. The synchronous rectifier MOSFET is now controlled in diode emulation mode, hence conduction in the second quadrant is prohibited. The converter output voltage is applied to the negative input of the hysteretic comparator. The voltage on the reference input of the hysteretic comparator is the DAC output voltage with a
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IPM6210A
small addition of the clock frequency pulses. Synchronization of the upper MOSFET turn-on pulses with the main clock enables seamless transition between the operation modes. Several scenarios of the current protection circuit behavior are possible.
Operation During Processor Mode Changes
The PWM1 controller is specially designed to provide "on the fly" automatic core voltage changes required by some advanced processors for mobile applications. Dual core voltage and operation frequency scaling allows for significant power savings without sacrificing system performance in battery operation mode. As processor mode changes can happen when chip is in PWM or hysteretic mode, measures were taken to provide equally fast response to these changes. As soon as a DAC code change is received, the chip is forced into PWM mode till transition completes regardless of the load level. Operating the controller in the synchronous PWM mode allows faster output voltage transitions especially when a downward output voltage change is commanded.
VIO 1
IIO
2
Ch1 50mV
Ch2 500mA
M50ms
FIGURE 9. I/O CONVERTER LOAD TRANSIENT IN PWM MODE
I/O Converter Architecture
The I/O converter architecture is close to that of the core converter. It has the same mode control logic and can operate in a constant frequency PWM mode or in hysteretic mode depending on the load level, but its structure is much simpler mainly because of absence of the differential input amplifier and the DAC. This controller is synchronized to the same clock as the core converter, but 180 degrees out-of-phase. Thus, some reduction of the input current ripple is achieved. Some performance curves of I/O converter are shown on Figure 9 and Figure 10.
VIO 1
IIO
Gate Control Logic
The gate control logic translates generated PWM signals into the MOSFETs gate drive signals providing necessary amplification, level shift and shoot-trough protection. Also, it helps to optimize the IC performance over a wide range of the operational conditions. As MOSFET switching time can very dramatically from type to type and with input voltage variation, the gate control logic provides adaptive dead time by monitoring gate voltages of both upper and lower MOSFETs.
2
Ch1 50mV
Ch2 500mA
M50s
FIGURE 10. I/O CONVERTER LOAD TRANSIENT WITH MODE CHANGE
Protections
All three outputs are monitored and protected against extreme overload, short circuit and undervoltage conditions. Both PWM outputs are monitored and protected from overvoltage conditions. A sustained overload on any output latches-off all the converters and sets the PGOOD pin low. The chip operation can be restored by cycling VCC voltage or EN pin.
If load step is strong enough to pull output voltage lower than the undervoltage threshold, chip shuts down. If the output voltage sag does not reach the undervoltage threshold but the current exceeds the overcurrent threshold, the pulse skipping circuit is activated. This breaks the output voltage regulation and limits the current supplied to the load. Because of the nature of the current sensing technique, and to accommodate a wide range of the rDS(ON) variation, the value of the threshold should represent overload current about 180% of the nominal value. To decrease current protection circuit noise susceptibility, a time delay circuit (8:1 counter which counts the clock cycles) is activated when the overcurrent condition is detected for the first time. If after the delay the overcurrent condition persists, the converter shuts down. If not - normal operation is restored.
Overcurrent Protection
Both PWM controllers use the lower MOSFET's on-resistance - rDS(ON) to monitor the current for protection against shorted outputs. The sensed voltage drop after amplification is compared with an internally set threshold.
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IPM6210A
The overcurrent protection circuit trips when the peak value of the lower MOSFET current is higher than the one obtained from the following equation.
I th ( R CS + 100 ) IOC = -----------------------------------------------R D SON
Output Inductor Selection
The minimum practical output inductor value is the one that keeps inductor current just on the boundary of continuous conduction at some minimum load. The industry standard practice is to choose the minimum current somewhere from 10% to 25% of the nominal current. At light load, IPM6210A PWM controllers automatically switch to a hysteretic mode of operation to sustain high efficiency. It is suggested that transition to hysteretic mode occur before inductor current becomes discontinuous. The following equations help to choose proper value of the output filter inductor.
I = 2x Imin Vout I = ----------------ESR Vin - Vo ut Vout L = ---------------------------- x -----------Vin Fs x I
where: RCS is a resistor from ISEN pin to PHASE pin; Ioc is the desired overload current trip level; rDS(ON) is either rDS(ON) of the lower MOSFET, or the value of the optional current sense resistor; Ith is the threshold of the current protection circuitry (140A). In the linear regulator the maximum current of the integrated power device is actively limited to 250mA that eventually creates an undervoltage condition and sets the fault latch.
Overvoltage Protection
During operation, severe load dump or a short of an upper MOSFET can cause the output voltage to increase significantly over normal operation range. When the output exceeds the overvoltage threshold of 115% of the DAC voltage (1.7V for PWM2), the overvoltage comparator forces the lower gate driver high and turns the lower MOSFET on. This will pull down the output voltage and eventually blow the battery fuse. As soon as output voltage drops below the threshold, OVP comparator is disengaged. Such an OVP scheme provides soft crowbar function and does not interfere with on-the-fly VID code changes. During downward changes in the converter output voltage, the condition where the OVP threshold is set before the new value of the output voltage is reached is permissible and harmless. Also, it does not invert output voltage when activated, a common problem for OVP schemes with a latch. Overvoltage protection is not provided for the linear regulator.
1
1.60VCORE
2 3 4
1.50VIO 2.50VCLK EN
Ch1 500mV Ch3 1.0V
Ch2 500mV Ch4 5.0V
M1.0ms
FIGURE 11. SHUTDOWN WAVEFORMS
Output Capacitor Selection
An output capacitor serves two major functions in a switching power supply. Along with an inductor it filters the sequence of pulses produced by the switcher and supply the load transient currents. The filtering requirements are a function of the switching frequency and the ripple current allowed, and are usually easy to satisfy in high frequency converters. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. Modern microprocessors produce transient load rates in excess of 10A/s. High frequency ceramic capacitors placed beneath the processor socket initially supply the transient and reduce the slew rate seen by the bulk capacitors. The bulk capacitor values are generally determined by the total allowable ESR rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the processor power pins as physically possible. Consult with the processor manufacturer for specific decoupling requirements. Use only specialized low-ESR electrolytic capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor's ESR will determine the
Shutdown
When EN (pin 20) is pulled down, the chip is disabled and enters a low-current state. Both high-side and low-side gate drivers are turned off. This control scheme produces no negative output voltage at shutdown, as shown in Figure 11. A rising edge on EN clears the fault latch.
Thermal Shutdown
The chip incorporates an over temperature protection circuit that shuts all the outputs down when the die temperature of 150oC is reached. Normal operation restores at die temperatures below 125oC through the full soft-start cycle.
Design Procedure and Component Selection Guidelines
As an initial step, define operating voltage range, minimum and maximum load currents for each controller.
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IPM6210A
output ripple voltage and the initial voltage drop after a transient. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor.
Layout Considerations
Switching converters, even during normal operation, produce short pulses of current which could cause substantial ringing and be a source of EMI pollution if layout constrains are not observed.
TABLE 2 COMPONENT Maximum CPU Current Inductor CIRCUIT 1 8.0A CIRCUIT 2 12.0A CIRCUIT 3 18.0A
MOSFET Selection and Considerations
Requirements for the upper and lower MOSFETs are different in mobile applications. The reason for that is the 10:1 difference in conduction time of the lower and the upper MOSFETs driven by a difference between the input voltage which is nominally in the range from 8V to 20V, while nominal output voltage is about 1.5V. Requirements for the lower MOSFET are simpler than those to the upper one. The lower the rDS(ON) of this device, the lower the conduction losses, the higher the converter's efficiency. Switching losses and gate drive losses are not significant because of zero-voltage switching conditions inherent for this device in the buck converter. Low reverse recovery charge of the body diode is important because it causes shoot-trough current spikes when the upper MOSFET turns on. Also, important is to verify that the lower MOSFET gate voltage does not reach threshold when high dV/dt transition occurs on the phase node. To minimize this effect, IPM6210A has a low, 0.8 typical, low side driver pull-down resistance. Requirements to the upper MOSFET rDS(ON) are less stringent than to the lower MOSFET because its conduction time is significantly shorter so switching losses can dominate especially at higher input voltages. It is recommended to have equal conduction and switching losses in the upper MOSFET at the nominal input voltage and load current. Then the maximum of the converter efficiency is tuned to the operating point where it is most desired. Also, this provides the most cost effective solution. Precise calculation of power dissipation in the MOSFETs is very complex because many parameters affecting turn-on and turn-off times such as gate reverse transfer charge, gate internal resistance, body diode reverse recovery charge, package and layout impedances and their variation with the operation conditions are not available to a designer. The following equations are provided only for rough estimation of the power losses and should be accompanied by a detailed breadboard evaluation. Attention should be paid to the input voltage extremes where power dissipation in the MOSFETs is usually higher.
Io 2 x r DS ( ON ) ( VOUT ) Io x V IN xFs x ton + toff P U PPER = ---------------------------------------------------------- + --------------------------------------------------------------V IN 2 VOUT P LOWER = Io 2 x r DS ( ON ) x 1 - --------------- VI N
0.8H 1.0H 2.0H Panasonic Panasonic Panasonic ETQP6F2R0BFA ETQP6F2R0BFA ETQP6F2R0BFA 6x270F 5x270F 3x270F Panasonic Panasonic Panasonic EEFUE0D271R EEFUE0D271R EEFUE0D271R or or Sanyo Sanyo 4x2R5TPC220M 6x2R5TPC220M HUF76112SK8 ITF86130SK8T 1.27k HUF76112SK8 2x ITF86130SK8T 1.00k 2x HUF76112SK8 2x ITF86130SK8T 1.50k
Output Capacitor
High-Side MOSFET Low-Side MOSFET Current-Input Resistor for
~6% Droop At VO = 1.6V
There are two sets of critical components in a DC-DC converter. The switching power components process large amounts of energy at high rate and though, usually appear to be a source of a noise, end a low power components responsible for bias and feedback functions, though appear to be mainly recipients of the noise. The situation with the IPM6210A control IC is even more critical as it provides control functions for two independent converters and poor layout design could lead to cross talk between the converters and result in degradation in the performance. A multi-layer printed circuit board is recommended. Dedicate one solid layer for a ground plane. Dedicate another solid layer as a power plane and break this plane into smaller island of common voltage levels. Notice all the nodes that are subjected to high dV/dt voltage swing as PHASE1,2 nodes, for example. All surrounding circuitry will tend to couple the noise from these nodes trough stray capacitance. Do not oversize copper traces connected to these nodes. Do not place traces connected to the feedback components adjacent to these traces. Keep the wiring traces from the control IC to the MOSFET gate and source as short as possible and capable to handle peak currents up to 2A. Minimize the area within the gatesource path to reduce stray inductance and eliminate parasitic ringing at the gate. Locate small critical components like the soft-start capacitor and current sense resistors as close, as possible to the respective pins of the IC.
Table 2 provides some component information for several typical applications.
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IPM6210A IPM6210A DC-DC Converter Application Circuit
Figure 12 shows an application circuit of a power supply for a notebook PC microprocessor system. The power supply provides the microprocessor core voltage (VCORE), the I/O voltage (VI/O) and the clock generator voltage (VCLK) from +5.6-24VDC , +5VDC and +3.3VDC .
+5V VIN +5.6V-24.0V GND
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C1 + 56F
C4 1F
C5-6 2x1F
CR1 BAT54WT1 VCC VBAT BOOT2 C2 0.22F Q1 HUF76112SK8 19 3 28 21 25 PGOOD BOOT1 UGATE1
CR2 BAT54WT1
VGATE
UGATE2 PHASE2
4 5
24 23
Q3 HUF76112SK8
C7 0.22F
L1 VI/O (1.5V) + 10H C3 330F Q2 HUF76112SK8
R1 500
IPM6210A
ISEN2 6 22
ISEN1 R2 1K
L2 2H Q4 ITF86130SK8 C8 + 3x680F
VCORE (0.925 TO 2.0V)
LGATE2 PGND2 VSEN2
1 2 12
27 26
LGATE1 PGND1
+ C9 8x1F 2x10F
17 16
VSEN1 VRTN1 FROM CPU CORE
VR_ON
EN 20
11 10 +3.3VIN VCLK (2.5V) + V3IN 9 13 8 7 VSEN3 C4 10F 14 18
VID0 VID1 VID2 VID3 VID4 SOFT C10 0.22F
VID0 VID1 VID2 VID3 VID4
15 GND
FIGURE 12. APPLICATION CIRCUIT
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IPM6210A Shrink Small Outline Plastic Packages (SSOP)
N INDEX AREA E -B1 2 3 L SEATING PLANE -AD -CA 0.25 0.010 h x 45o GAUGE PLANE H 0.25(0.010) M BM
M28.15
28 LEAD SHRINK NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 B C D MIN 0.053 0.004 0.008 0.007 0.386 0.150 MAX 0.069 0.010 0.061 0.012 0.010 0.394 0.157 MILLIMETERS MIN 1.35 0.10 0.20 0.18 9.81 3.81 MAX 1.75 0.25 1.54 0.30 0.25 10.00 3.98 NOTES 9 3 4 5 6 7 8o Rev. 0 2/95
A1 0.10(0.004) A2 C
E e H h L N
e
B 0.17(0.007) M C AM BS
0.025 BSC 0.228 0.0099 0.016 28 0o 8o 0.244 0.0196 0.050
0.635 BSC 5.80 0.26 0.41 28 0o 6.19 0.49 1.27
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of "B" dimension at maximum material condition. 10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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